Reducing metal gate overhang by forming a top-wide bottom-narrow dummy gate electrode

ABSTRACT

A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

CROSS-REFERENCE

This application is a divisional of U.S. application Ser. No.15/420,580, filed Jan. 31, 2017 which claims benefit of U.S. ProvisionalApplication No. 62/405,301, filed Oct. 7, 2016, both of which are hereinincorporated by reference in their entirety.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapidgrowth. Technological advances in IC materials and design have producedgenerations of ICs where each generation has smaller and more complexcircuits than the previous generation. However, these advances haveincreased the complexity of processing and manufacturing ICs and, forthese advances to be realized, similar developments in IC processing andmanufacturing are needed. In the course of integrated circuit evolution,functional density (i.e., the number of interconnected devices per chiparea) has generally increased while geometry size (i.e., the smallestcomponent (or line) that can be created using a fabrication process) hasdecreased.

To facilitate the semiconductor device scaling down process, metal gateelectrodes may be used instead of conventional polysilicon electrodes.The formation of the metal gate electrodes may involve a gatereplacement process, in which a dummy gate electrode is removed to forman opening in its place, and the opening is subsequently filled by metalmaterials to form the metal gate electrode. However, conventional gatereplacement processes may leave an overhang in the opening, which mayimpede the filling of the opening by the metal material. As such, voidsmay form in the metal gate, which degrades semiconductor deviceperformance.

Therefore, while existing gate replacement processes have been generallyadequate for their intended purposes, they have not been entirelysatisfactory in every aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

FIG. 1 is a diagrammatic cross-sectional side view of a semiconductordevice at a stage of fabrication according to various embodiments of thepresent disclosure.

FIG. 2 is a diagrammatic cross-sectional side view of a semiconductordevice at a stage of fabrication according to various embodiments of thepresent disclosure.

FIG. 2A is a diagrammatic cross-sectional side view of a semiconductordevice at a stage of fabrication according to various embodiments of thepresent disclosure.

FIG. 3 is a diagrammatic cross-sectional side view of a semiconductordevice at a stage of fabrication according to various embodiments of thepresent disclosure.

FIG. 4 is a diagrammatic cross-sectional side view of a semiconductordevice at a stage of fabrication according to various embodiments of thepresent disclosure.

FIG. 5 is a diagrammatic cross-sectional side view of a semiconductordevice at a stage of fabrication according to various embodiments of thepresent disclosure.

FIG. 6 is a diagrammatic cross-sectional side view of a semiconductordevice at a stage of fabrication according to various embodiments of thepresent disclosure.

FIG. 7 illustrates several suitable cross-sectional profiles for thedummy gate electrodes fabricated according to various embodiments of thepresent disclosure.

FIG. 8 is a flow chart of a method for fabricating a semiconductordevice in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

It is understood that the following disclosure provides many differentembodiments, or examples, for implementing different features of thepresent disclosure. Specific examples of components and arrangements aredescribed below to simplify the present disclosure. These are, ofcourse, merely examples and are not intended to be limiting. Forexample, the formation of a first feature over or on a second feature inthe description that follows may include embodiments in which the firstand second features are formed in direct contact, and may also includeembodiments in which additional features may be formed between the firstand second features, such that the first and second features may not bein direct contact. In addition, the present disclosure may repeatreference numerals and/or letters in the various examples. Thisrepetition is for the sake of simplicity and clarity and does not initself dictate a relationship between the various embodiments and/orconfigurations discussed. Moreover, various features may be arbitrarilydrawn in different scales for the sake of simplicity and clarity.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. For example, if the device in the figures is turned over,elements described as being “below” or “beneath” other elements orfeatures would then be oriented “above” the other elements or features.Thus, the exemplary term “below” can encompass both an orientation ofabove and below. The apparatus may be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein may likewise be interpreted accordingly.

As semiconductor fabrication technology advances, metal gate transistorshave been used in recent years to enhance the performance of ICs. Metalgate transistors use metal gate electrodes instead of the conventionalpolysilicon gate electrodes. The fabrication processing of metal gatetransistors may involve a gate replacement process, where a polysilicondummy gate electrode is replaced by a metal gate electrode after theformation of the source/drain regions. However, due to the scaling downof semiconductor devices, critical dimensions (e.g., a width of thegate) have become increasingly small, while an aspect ratio (e.g., aratio between the height of the gate and the width of the gate) mayincrease. The small CD and the high aspect ratio of the gate may lead toproblems or difficulties in replacing the polysilicon dummy gateelectrode with the metal gate electrode. For example, the small CD andthe high aspect ratio may lead to an “overhang” situation, where theopening (formed by the removal of the dummy polysilicon gate electrode)is partially blocked. This may result in voids in the metal gateelectrode subsequently formed in the opening. The voids in metal gateelectrodes degrade the performance of the transistor device (e.g.,excessive resistivity), which is undesirable.

To overcome the problems discussed above, the present disclosure uses anovel etching process in the formation of the dummy gate electrodes. Thenovel etching processes change the profile/shape of the dummy gateelectrodes, such that a top portion of the dummy gate electrode is widerthan (or at least not narrower than) a bottom portion of the dummy gateelectrode. This is in stark contrast to the conventionally-fabricateddummy gate electrodes, where the top portion of the dummy gate electrodeis narrower than the bottom portion of the dummy gate electrode. As willbecome more apparent based on the discussions below, the unique profileof the dummy gate electrodes will cause the opening (formed by theirremoval) to be more easily filled by metal materials in later processes,which leads to substantially void-free metal gate electrodes. Thedetails of the present disclosure are discussed below with reference toFIGS. 1-8.

FIGS. 1-6 are simplified diagrammatic fragmentary cross-sectional sideviews of a semiconductor device 35 during various fabrication stages.The semiconductor device 35 may be a part of an integrated circuit (IC)chip, system on chip (SoC), or portion thereof. It may include variouspassive and active microelectronic devices such as resistors,capacitors, inductors, diodes, metal-oxide semiconductor field effecttransistors (MOSFET), complementary metal-oxide semiconductor (CMOS)transistors, laterally diffused MOS (LDMOS) transistors, high power MOStransistors, or other types of transistors. It is understood that FIGS.1-6 have been simplified for a better understanding of the inventiveconcepts of the present disclosure. Accordingly, it should be noted thatadditional processes may be provided before, during, and after theprocesses shown in FIGS. 1-6 to complete the fabrication of thesemiconductor device 35, and that some other processes may only bebriefly described herein.

Referring to FIG. 1, a semiconductor device 35 has a substrate 40. Thesubstrate 40 is a silicon substrate doped with a P-type dopant such asboron (for example a P-type substrate). Alternatively, the substrate 40could be another suitable semiconductor material. For example, thesubstrate 40 may be a silicon substrate that is doped with an N-typedopant such as phosphorous or arsenic (an N-type substrate). Thesubstrate 40 may alternatively be made of some other suitable elementarysemiconductor, such as diamond or germanium; a suitable compoundsemiconductor, such as silicon carbide, indium arsenide, or indiumphosphide; or a suitable alloy semiconductor, such as silicon germaniumcarbide, gallium arsenic phosphide, or gallium indium phosphide.Further, the substrate 40 could include an epitaxial layer (epi layer),may be strained for performance enhancement, and may include asilicon-on-insulator (SOI) structure.

Still referring back to FIG. 1, shallow trench isolation (STI) features45 are formed in the substrate 40. The STI features 45 are formed byetching recesses (or trenches) in the substrate 45 and filling therecesses with a dielectric material. In the present embodiment, thedielectric material of the STI features 45 includes silicon oxide. Inalternative embodiments, the dielectric material of the STI features 45may include silicon nitride, silicon oxy-nitride, fluoride-dopedsilicate (FSG), and/or a low-k dielectric material known in the art. Inother embodiments, deep trench isolation (DTI) features may be formed inplace of, or in combination with, the STI features 45.

An interfacial layer may be optionally formed over the substrate 40. Theinterfacial layer may be formed by an atomic layer deposition (ALD)process and includes silicon oxide (SiO₂).

A gate dielectric layer 60 is formed over the upper surface of substrate40 (or over the interfacial layer if the interfacial layer is formed).The gate dielectric layer 60 may be formed by an ALD process in someembodiments. In some embodiments, the gate dielectric layer 60 includesa high-k dielectric material. A high-k dielectric material is a materialhaving a dielectric constant that is greater than a dielectric constantof SiO₂, which is approximately 4. In an embodiment, the gate dielectriclayer 60 includes hafnium oxide (HfO₂), which has a dielectric constantthat is in a range from approximately 18 to approximately 40. Inalternative embodiments, the gate dielectric layer 60 may include one ofZrO₂, Y₂O₃, La₂O₅, Gd₂O₅, TiO₂, Ta₂O₅, HfErO, HfLaO, HfYO, HfGdO, HfAlO,HfZrO, HfTiO, HfTaO, and SrTiO.

A capping layer 70 is formed over the gate dielectric layer 60. Theformation of the capping layer 70 includes one or more deposition andpatterning processes. In some embodiments, the capping layer 70 includesa lanthanum oxide material (LaO_(x), where x is an integer), but it isunderstood that the capping layer may include other suitable materials(e.g., rare earth oxides such as LaOx, GdOx, DyOx, or ErOx) in otherembodiments. In some embodiments, the material of the capping layer maybe selected so that it can help tune a work function of a transistorgate (to be formed later), such that a desired threshold voltage may beachieved for the transistor. It is understood that the gate dielectriclayer 60 and the capping layer 70 are formed over both an NMOStransistor region and a PMOS transistor region at this stage offabrication. In some embodiments, a thickness of the capping layer is ina range from about 5 Angstroms to about 20 Angstroms.

A polysilicon layer 80 is formed over the capping layer 70. Thepolysilicon layer 80 will be patterned later to form dummy gateelectrodes. A patterned hard mask layer 90 is formed over thepolysilicon layer 80. In some embodiments, the patterned hard mask layer90 includes multiple layers having different material compositions. Forexample, the patterned hard mask layer 90 may include a silicon nitridelayer formed over the polysilicon layer 80, and it may also include asilicon oxide layer formed over the silicon nitride layer. The patternedhard mask layer 90 may be patterned through a photolithography processinto a plurality of segments, such as segments 90A and 90B.

Referring now to FIG. 2, the segments 90A and 90B of the patterned hardmask layer 90 may be used as masks to define gate structures oftransistors. In more detail, an etching process 100 is performed to etchthe polysilicon layer 80. The segments 90A and 90B of the patterned hardmask layer 90 serve as etching masks in the etching process 100 toprotect portions of the layers below (including the polysilicon layer80, the capping layer 70, and the gate dielectric layer 60) from beingetched.

The etching process 100 forms gate structures 120A and 120B separated byan opening 130, where the gate structure 120A includes the segment 90A,a remaining portion 80A of the polysilicon layer, a remaining portion70A of the capping layer, and a remaining portion of the gate dielectriclayer 60A, and the gate structure 120B includes the segment 90B, aremaining portion 80B of the polysilicon layer, a remaining portion 70Bof the capping layer, and a remaining portion of the gate dielectriclayer 60B. It is understood that the remaining portions 80A and 80B ofthe polysilicon layer serve as dummy gate electrodes herein and will beremoved in a dummy gate replacement process later.

According to embodiments of the present disclosure, the etching process100 is configured to form dummy gate electrodes 80A-80B whose sidewallprofiles are sloped inwards. For example, the dummy gate electrode 80A(or 80B) has a lateral dimension 140 near its upper surface and alateral dimension 141 nears its bottom surface. The lateral dimension140 is greater than or equal to (or no less than) the lateral dimension141. In some embodiments, the lateral dimension 140 is greater than thelateral dimension 141 by at least 5%, for example by about 5%-20%.Consequently, the dummy gate electrodes 80A and 80B shown in FIG. 2 eachhave a cross-sectional profile/shape that loosely resembles an inverseor upside-down trapezoid, though it is understood that in real worldfabrication, the sidewall surfaces of the dummy gate electrodes 80A-80Bmay not be as straight or smooth as they are shown in FIG. 2, since FIG.2 provides merely a simplified illustration.

This upside-down trapezoidal shape of the dummy gate electrodes 80A-80Bis obtained by configuring the lateral etching characteristics of theetching process 100. For example, the etching process 100 may beconfigured to have increasingly stronger lateral etching characteristicsas the etching progresses deeper (i.e., closer to the substrate 40). Insome embodiments, the etching process 100 includes a plurality ofetching steps, where each etching step has an associated lateral etchingrate, and that each subsequent etching step has a greater lateraletching rate than a previous etching step.

The etching process (or the various etching steps included therein) mayinclude simultaneously applying a high electronegativity etchant and achlorine etchant inside an etching chamber, with the wafer undergoingthe etching process 100 placed therein. In some embodiments, thechlorine etchant may include a Cl₂ gas or plasma with a flow rate in arange between about 30 standard cubic centimeters per minute (sccm) andabout 36 sccm, and the high electronegativity etchant may include afluorine-containing gas or plasma with a flow rate in a range betweenabout 80 sccm to about 120 sccm. As non-limiting examples, thefluorine-containing gas or plasma may include a fluorine-rich materialsuch as C_(x)F_(y), (where x and y are positive integers, for exampleCF₄ or C₂F₆), CHF₃, HBr, or NF₃. The etching mechanism is as follows:

-   -   The fluorine-containing etchant reacts with a surface oxide        (e.g., formed on the sidewalls of the dummy gate electrodes        80A-80B as they are being etched) to produce silicon-containing        and oxygen-containing gases that can be removed from the etching        chamber by a purging mechanism. For example, with CF₄ as an        etchant, the surface oxide may react with CF₄ according to the        following chemical formula: SiO₂+CF₄=>SiF₄+CO₂, where SiF₄+CO₂        are gases that can be removed from the etching chamber.    -   The chlorine-containing etchant reacts with the polysilicon        material of the dummy gate electrodes 80A-80B to form another        gas (e.g., SiCl_(x), where x is a positive integer) that can be        removed from the etching chamber by a purging mechanism.

The flow rate of the fluorine-containing etchant may be correlated withthe lateral etching characteristics of the etching process 100. Forexample, increasing the flow rate of the fluorine-containing etchantenhances the lateral etching rate of the etching process 100. As such,to achieve the desired top-wide bottom-narrow profile of the dummy gateelectrodes 80A-80B, the etching process 100 may be configured such thatthe fluorine content is increased (e.g., by increasing the flow rate ofthe fluorine-containing etchant) as deeper and deeper portions of thepolysilicon layer 80 are etched. For example, in a first etching stepperformed to etch a top portion of the dummy gate electrode 80A/80B, theflow rate of the fluorine-containing etchant may be configured to be Xsccm. In a second etching step performed to etch a middle portion of thedummy gate electrode 80A/80B, the flow rate of the fluorine-containingetchant may be configured to be Y sccm. In a third etching stepperformed to etch a bottom portion of the dummy gate electrode 80A/80B,the flow rate of the fluorine-containing etchant may be configured to beZ sccm. Z is greater than Y, and Y is greater than X, and X is no lessthan 80 sccm. Of course, the three etching steps are merely examples,and the etching process 100 may be configured to have two etching stepsor four or more etching steps in other embodiments, as long as thefluorine content in the etchant increases with each etching step.

Due to the rich fluorine content of the etchant used herein, fluorineparticles 150 may remain on the surfaces of the substrate 40, the STIfeatures 45, or even on the side surfaces of the gate structures120A-120B after the etching process 100 has been completed. Due to thehigh fluorine content in the etching process 100, these fluorineparticles may still remain after various cleaning processes areperformed. In other words, the removal of the fluorine particles 150 maynot be complete, and some traces of them may be found in an actuallyfabricated semiconductor device. The presence of the fluorine particles150 may be detected by certain semiconductor fabrication inspectiontools. The remnants of fluorine may be evidence that an etching processsimilar to the etching process 100 according to the present disclosureis used to fabricate the semiconductor device.

In some embodiments, a passivation gas may also be applied along withthe etchant to facilitate the formation of the dummy gate electrodes80A-80B with the top-wide bottom-narrow profiles. The passivation gasforms a passivation material on the exposed surfaces of the polysiliconlayer 80 as the etching process 100 takes place. The passivationmaterial helps prevent further etching of the polysilicon material. Asimplified example of this is shown in FIG. 2A. Referring to FIG. 2A, asa top portion of the polysilicon layer 80 is etched, the passivation gasforms the passivation materials 170A-170B on the sidewalls of the dummygate electrodes 80A-80B near the top. This will allow the etchingprocess 100 to progress downwards and continue the lateral etching ofthe lower portions of the polysilicon layer 80 without further lateraletching of the dummy gate electrodes 80A-80B at the top, because theyare protected by the passivation materials 170A-170B.

It is also noted that since the dummy gate electrodes 80A-80B havetop-wide bottom-narrow profiles, the opening 130 separating the dummygate electrodes 80A-80B has a top-narrow and bottom-wide profile.

Referring now to FIG. 3, gate spacers 190A-190B are formed on sidewallsof the gate structures 120A-120B. The gate spacers 190A-190A include adielectric material. In some embodiments, the gate spacers 190A-190Binclude silicon nitride. In alternative embodiments, the gate spacers190A-190B may include silicon oxide, silicon carbide, siliconoxy-nitride, or combinations thereof.

Thereafter, heavily doped source and drain regions 200A and 200B (alsoreferred to as S/D regions) are formed in the NMOS and PMOS portions ofthe substrate 40, respectively. The S/D regions 200A-200B may be formedby an ion implantation process, or by a diffusion process. N-typedopants such as phosphorus or arsenic may be used to form the NMOS S/Dregions 200B, and P-type dopants such as boron may be used to form thePMOS S/D regions 200A. As is illustrated in FIG. 3, the S/D regions200A-200B are aligned with the outer boundaries of the gate spacers190A-190B, respectively. Since no photolithography process is requiredto define the area or the boundaries of the S/D regions 200A-200B, itmay be said that the S/D regions 200A-200B are formed in a“self-aligning” manner. One or more annealing processes are performed onthe semiconductor device 35 to activate the S/D regions 200A-200B. It isalso understood that in some embodiments, lightly-doped source/drain(LDD) regions may be formed in both the NMOS and PMOS regions of thesubstrate 40 before the gate spacers 190A-190B are formed. For reasonsof simplicity, the LDD regions are not specifically illustrated herein.

Referring now to FIG. 4, an inter-layer (or inter-level) dielectric(ILD) layer 220 is formed over the substrate 40 and the gate structure220. The ILD layer 220 may be formed by chemical vapor deposition (CVD),high density plasma CVD, spin-on, sputtering, or other suitable methods.The ILD layer 220 fills the opening 130, for example. In an embodiment,the ILD layer 220 includes silicon oxide. In other embodiments, the ILDlayer 220 may include silicon oxy-nitride, silicon nitride, or a low-kmaterial. A polishing process (for example achemical-mechanical-polishing (CMP) process) may be performed on the ILDlayer 220 to planarize the ILD layer 220. The polishing is performeduntil top surfaces of the dummy gate electrodes 80A of gate structures120A-120B are exposed. The hard masks 90A-90B are also removed by thepolishing process.

Still referring to FIG. 4, after the formation of the ILD layer 200 andthe subsequent planarization thereof, an etching process 260 isperformed to remove the dummy gate electrodes 80A-80B. In someembodiments, the etching process 260 may include a dry etching process.The gate dielectric layer 60A-60B and the capping layer 70A-70B are notremoved by the etching process 260 in the illustrated embodiment. As aresult of the etching process 260, trenches or openings 270A-270B areformed. Since the dummy gate electrodes 80A-80B are formed to have aprofile such that it is wider at the top and narrower at the bottom(e.g., dimension 140>=dimension 141), the trenches 270A-270B alsoinherit this profile, meaning that the trenches may also have a widerlateral dimension 140 at its top and a narrower dimension 141 at itsbottom. This specifically-configured shape/profile of the trenches270A-270B makes them easier to fill, even if the trenches 270A-270 havesmall CDs and high aspect ratios.

Referring now to FIG. 5, a plurality of metal deposition processes 280are performed to deposit a metal layer 290 and a metal layer 291. Themetal layer 290 is formed over the exposed surfaces of the ILD layer220, the spacers 190A-190B, the capping layer 70A-70B, and partiallyfill the trenches 270A-270B. The metal layer 291 is formed over themetal layer 290. In some embodiments, the metal layer 290 includes awork function metal, which helps tune a work function of a MOStransistor, such that a desired threshold voltage may be achieved forthe MOS transistor. In some embodiments, the work function metal mayinclude a P-type work function metal, which may contain tungsten (W),tungsten nitride (WN), or tungsten aluminum (WAl) as examples. In someembodiments, the work function metal may include an N-type work functionmetal, which may contain titanium nitride (TiN) as an example.

In some embodiments, the metal layer 291 includes a fill metal, whichserves as the main conductive portion of the gate electrode. In someembodiments, the fill metal layers contain tungsten (W), aluminum (Al),titanium (Ti), Copper (Cu), or combinations thereof. In otherembodiments, a blocking layer may be formed between the fill metal layerand the work function metal, so as to reduce diffusion between the workfunction metal and the fill metal. The blocking layer may include TiN orTaN. Furthermore, a wetting layer (e.g., containing Ti) may beoptionally formed between the blocking layer and the fill metal layer toenhance the formation of the fill metal layer.

Referring now to FIG. 6, a planarization process 300 is performed topolish the metal layers 291 and 290 until the upper surfaces of themetal layers 291 and 290 are substantially coplanar with the uppersurface of the ILD layer 220. In some embodiments, the planarizationprocess 300 includes a CMP process. After the planarization process 300is performed, the remaining portions 290A and 291A of the metal layersfilling the trench 270A collectively constitute a metal gate electrodefor the PMOS, and the remaining portions 290B and 291B of the metallayers filling the trench 270B collectively constitute a metal gateelectrode for the NMOS.

For reasons discussed above, the profile of the trenches 270A-270B allowfor the metal layers 290-291 to easily fill in the trenches 270A-270Bwithout gaps or voids. In contrast, in conventional gate replacementprocesses, the metal gate formation may be impeded by overhangs thatexist near the upper portions of the openings (i.e., openings formed bythe removal of the dummy gate electrodes). Overhangs are formed as aresult of conventional fabrication, because of the tapered shape of theetched dummy gate electrodes where the top is narrower than the bottom.Thus, the resulting trench would also be narrower at the top and widerat the bottom, thereby creating the overhangs. The overhangs may causedifficulties in the metal layers filling the trenches, thus leading tovoids/gaps within the metal electrodes. This problem is overcome by thepresent disclosure, because the etching process 100 discussed above withreference to FIG. 2 is specifically configured (e.g., by increasing thelateral etching rate as the etching gets deeper) to form dummy gateelectrodes 80A-80B that are wider at the top and narrower at the bottom,thereby allowing for easy filling of the trenches 270A-270B withoutsubstantial voids or gaps in the formed metal electrodes. Thus,semiconductor performance is improved.

It is understood that although FIGS. 2-6 illustrate an approximatelyinverse trapezoidal profile (i.e., loosely resembling an upside-downtrapezoid) for the etched dummy gate electrodes 80A-80B (and thereforethe same profile for the metal gate electrodes that replace the dummygate electrodes), this particular profile/shape is not required but canbe changed in different embodiments. For example, FIG. 7 illustratesseveral other suitable cross-sectional profiles/shapes 400-405 for thedummy gate electrodes 80A-80B (and thus the metal gate electrodes). Theprofile 400 is shaped similar to a rectangle where a lateral dimensionand its top and a lateral dimension at its bottom are similar to oneanother. The profile 401 is shaped to have side surfaces that eachinclude a concave segment and a convex segment. The profile 402 isshaped to have more curved or rounded sidewall surfaces. The profile 403is shaped similar to two combined rectangles where an upper rectangle iswider than a bottom rectangle. The profile 404 is shaped similar tothree combined rectangles where an upper rectangle is wider than amiddle rectangle, which is wider than a bottom rectangle. The profile405 is similar to two combined upside-down trapezoids, where a toptrapezoid is wider than a bottom trapezoid.

For all the profiles 400-405, they have the common factor that thelateral dimension at the top is greater than or equal to the lateraldimension at the bottom. Again, this is configured to allow for easyfilling to form void-free metal gate electrodes. These profiles orshapes 400-405 shown in FIG. 7 can be achieved by tuning the processrecipes or process parameters of the etching process 100 discussedabove. Indeed, other suitable profiles/shapes (not illustrated herein)may also be obtained for the dummy gate electrodes (and thus the metalgate electrodes) according to the various aspects of the presentdisclosure.

The gate replacement process discussed above pertain to a “gate-last”process, where the high-k gate dielectric is formed, and the dummy gateelectrode is formed and then replaced by a metal gate electrode.However, it is understood that the various aspects of the presentdisclosure may also apply to a “high-k last” gate replacement process aswell. In a “high-k last” gate replacement process, instead of forming ahigh-k gate dielectric, a dummy gate dielectric (e.g., silicon oxide) isformed first, and a dummy gate electrode (e.g., polysilicon) is formedon the dummy gate dielectric. After the formation of the source/drainregions, the dummy gate dielectric is replaced by the high-k gatedielectric, and the dummy gate electrode is replaced by the metal gateelectrode. Regardless, the etching processes discussed above still applyto form the dummy gate electrode and the dummy gate dielectric to havethe profiles where the top is wider than the bottom, so as to facilitatethe filling of the openings with the high-k dielectric and the metalgate electrode. Furthermore, it is understood that the aspects of thepresent disclosure may apply to both “2-dimensional” planar devices or“3-dimensional” FinFET devices.

It is also understood that additional processes may be performed tocomplete the fabrication of the semiconductor device 35. For example,these additional processes may include formation of contact holes forthe gate structures, formation of interconnect structures (e.g., linesand vias, metal layers, and interlayer dielectric that provideelectrical interconnection to the device including the formed metalgate), deposition of passivation layers, packaging, testing, etc. Forthe sake of simplicity, these additional processes are not describedherein. It is also understood that some of the fabrication processes forthe various embodiments discussed above may be combined depending ondesign needs and manufacturing requirements.

FIG. 8 is a flowchart of a method 600 for fabricating a semiconductordevice in accordance with various aspects of the present disclosure. Themethod 600 includes a step 610 of forming a high-k gate dielectric layerover a substrate.

The method 600 includes a step 620 of forming a polysilicon layer overthe high-k gate dielectric layer.

The method 600 includes a step 630 of etching the polysilicon layer toform a dummy gate electrode having a top portion with a first lateraldimension and a bottom portion with a second lateral dimension. Thefirst lateral dimension is greater than, or equal to, the second lateraldimension.

The method 600 includes a step 640 of replacing the dummy gate electrodewith a metal gate electrode.

In some embodiments, the top portion of the dummy gate electrode isformed when the etching is performed with a first lateral etching rate,and the bottom portion of the dummy gate electrode is formed when theetching is performed with a second lateral etching rate greater than thefirst lateral etching rate.

In some embodiments, the etching comprises using a fluorine-containingetchant, and wherein the etching is performed by increasing a fluorinecontent of the etchant as the etching progresses deeper into thepolysilicon layer. In some embodiments, the increasing the fluorinecontent comprises increasing a flow rate of the fluorine-containingetchant. In some embodiments, the flow rate is no less than 80 standardcubic centimeters per minute (sccm) throughout the etching. In someembodiments, the flow rate is in a range between about 80 sccm and about120 sccm. In some embodiments, the etching comprises applying achorine-containing etchant simultaneously with the fluorine-containingetchant.

In some embodiments, the etching comprises applying a passivation gaswhen the top portion of the dummy gate electrode is etched.

In some embodiments, the etching is performed such that the dummy gateelectrode has a cross-sectional profile that resembles an upside-downtrapezoid.

In some embodiments, the first lateral dimension is greater than thesecond lateral dimension by at least 20%.

It is understood that additional process steps may be performed before,during, or after the steps 610-640 discussed above to complete thefabrication of the semiconductor device. For example, before thereplacing of the dummy gate electrode, the method 600 may include a stepof forming spacers on sidewalls of the dummy gate electrode, formingsource/drain regions in the substrate on opposite sides of the dummygate electrode, and forming an interlayer dielectric (ILD) over thesubstrate. Other process steps are not discussed herein for reasons ofsimplicity.

Based on the above discussions, it can be seen that the presentdisclosure offers advantages over conventional systems and methods offorming rail structures. It is understood, however, that otherembodiments may offer additional advantages, and not all advantages arenecessarily disclosed herein, and that no particular advantage isrequired for all embodiments. One advantage is the reduction orelimination of the overhang problem plaguing existing gate replacementprocesses. By configuring the etching process carefully, the resultingdummy gate electrode can be formed to have a profile such that it iswider at the top and narrow at the bottom. Once the dummy gate electrodeis removed, the trench formed in place of the removed dummy gateelectrode also inherits this top-wide and bottom-narrow profile. Thisprofile makes the trench easy to fill with a metal material, which isused to form the metal gate electrode. Consequently, the formed metalgate electrode is substantially void-free or gap-free, thereby havingimproved performance than conventionally formed metal gates.

One aspect of the present disclosure involves a method of fabricating asemiconductor device. A polysilicon layer is formed over a substrate.The polysilicon layer is etched to form a dummy gate electrode having atop portion with a first lateral dimension and a bottom portion with asecond lateral dimension. The first lateral dimension is greater than,or equal to, the second lateral dimension. The dummy gate electrode isreplaced with a metal gate electrode.

Another aspect of the present disclosure involves a method offabricating a semiconductor device. A gate dielectric layer is formedover a substrate. A dummy gate electrode layer is formed over the gatedielectric layer. The dummy gate electrode layer is etched with anetchant that contains fluorine and chlorine to form a dummy gateelectrode. The etching comprising increasing a fluorine content of theetchant as the etching progresses deeper into the dummy gate electrodelayer. Spacers are formed on sidewalls of the dummy gate electrode.Source/drain regions are formed in the substrate on opposite sides ofthe dummy gate electrode. The dummy gate electrode is replaced with ametal gate electrode.

Yet another aspect of the present disclosure involves a semiconductordevice. The semiconductor device includes a high-k gate dielectric layerdisposed over a substrate. The semiconductor device includes a metalgate electrode disposed over the high-k gate dielectric layer. The metalgate electrode has a top portion and a bottom portion. The bottomportion is located closer to the high-k gate dielectric layer than thetop portion. The top portion has a first lateral dimension. The bottomportion has a second lateral dimension. The first lateral dimension isno less than the second lateral dimension.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. A semiconductor device, comprising: a high-k gatedielectric layer disposed over a substrate; and a metal gate electrodedisposed over the high-k gate dielectric layer; wherein: the metal gateelectrode has a top portion and a bottom portion, the bottom portionbeing located closer to the high-k gate dielectric layer than the topportion; the top portion has a first lateral dimension; the bottomportion has a second lateral dimension; and the first lateral dimensionis no less than the second lateral dimension.
 2. The semiconductordevice of claim 1, further comprising fluorine-containing particlesdisposed on an upper surface of the substrate.
 3. The semiconductordevice of claim 1, wherein the metal gate electrode has across-sectional profile that resembles an upside-down trapezoid.
 4. Thesemiconductor device of claim 1, wherein the first lateral dimension isgreater than the second lateral dimension by at least 20%.
 5. Thesemiconductor device of claim 1, further comprising: a capping layerdisposed between the high-k gate dielectric layer and the metal gateelectrode.
 6. The semiconductor device of claim 5, wherein the cappinglayer contains a rare earth oxide.
 7. The semiconductor device of claim1, wherein a side surface of the metal gate electrode includes a concavesegment or a convex segment in a cross-sectional view.
 8. Thesemiconductor device of claim 7, wherein the side surface of the metalgate electrode includes both the concave segment and the convex segmentin the cross-sectional view.
 9. The semiconductor device of claim 1,wherein a side surface of the metal gate electrode includes a roundedprofile in a cross-sectional view.
 10. The semiconductor device of claim1, wherein the metal gate electrode has more sloped side surfaces thanthe high-k gate dielectric layer.
 11. The semiconductor device of claim1, wherein: the top portion has a first cross-sectional profile thatresembles a first rectangle; the bottom portion has a secondcross-sectional profile that resembles a second rectangle; and the firstrectangle is wider than the second rectangle.
 12. The semiconductordevice of claim 1, wherein: the top portion has a first cross-sectionalprofile that resembles a first trapezoid; the bottom portion has asecond cross-sectional profile that resembles a second trapezoid; andthe first trapezoid is wider than the second trapezoid.
 13. Thesemiconductor device of claim 1, wherein the metal gate electrodefurther includes a middle portion disposed between the top portion andthe bottom portion, wherein the middle portion has a third lateraldimension that is smaller than the first lateral dimension but greaterthan the second lateral dimension.
 14. A semiconductor device,comprising: a gate dielectric layer formed over a substrate; a gateelectrode formed over the gate dielectric layer, wherein the gateelectrode has sloped sidewalls; and fluorine-containing particlesdisposed over the substrate.
 15. The semiconductor device of claim 14,wherein an upper portion of the gate electrode is wider than a bottomportion of the gate electrode by at least 20%.
 16. The semiconductordevice of claim 14, wherein the gate electrode includes a plurality ofsegments, and wherein each segment has a wider lateral dimension thananother segment disposed therebelow.
 17. The semiconductor device ofclaim 14, wherein the gate dielectric layer contains a high-k gatedielectric material, and wherein the gate electrode contains one or moremetal materials, and wherein the semiconductor device further comprises:a capping layer disposed between the gate dielectric layer and the gateelectrode, wherein the capping layer contains LaO_(x), GdO_(x), DyO_(x),or ErO_(x).
 18. The semiconductor device of claim 14, wherein sidewallsof the gate dielectric layer are sloped differently than the sidewallsof the gate electrode.
 19. The semiconductor device of claim 14, whereinat least a portion of the sloped sidewalls of the gate electrode has acurved, concave, or convex cross-sectional profile.
 20. A semiconductordevice, comprising: a gate dielectric layer located over a substrate,wherein the gate dielectric layer includes a material having adielectric constant that is greater than a dielectric constant of SiO₂;a capping layer located over the gate dielectric layer, wherein thecapping layer includes a rare earth oxide material; a gate electrodelocated over the capping layer, wherein the gate electrode includes oneor more metal material, wherein an upper portion of the gate electrodeis at least as wide as a lower portion of the gate electrode; andfluorine-containing particles disposed over the substrate.